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We characterized resistance drift in phase change memory devices in the 80 K to 300 K temperature range by performing measurements on 20 nm thick, ∼70–100 nm wide lateral Ge₂Sb₂Te₅(GST) line cells. The cells were amorphized using 1.5–2.5 V pulses with ∼50–100 ns duration leading to ∼0.4–1.1 mA peak reset currents resulting in amorphized lengths between ∼50 and 700 nm. Resistance drift coefficients in the amorphized cells are calculated using constant voltage measurements starting as fast as within a second after amorphization and for 1 h duration. Drift coefficients range between ∼0.02 and 0.1 with significant device-to-device variability and variations during the measurement period. At lower temperatures (higher resistance states) some devices show a complex dynamic behavior, with the resistance repeatedly increasing and decreasing significantly over periods in the order of seconds. These results point to charge trapping and de-trapping events as the cause of resistance drift. 

Phase change memory (PCM) is a high speed, high endurance, high density non-volatile memory technology that utilizes chalcogenide materials such as Ge 2 Sb 2 Te 5 (GST) that can be electrically cycled between highly resistive amorphous and low resistance crystalline phases. The resistance of the amorphous phase of PCM cells increase (drift) in time following a power law [1] , which increases the memory window in time but limits in the implementation of multi-bit-per-cell PCM. There has been a number of theories explaining the origin of drift [1] - [4] , mostly attributing it to structural relaxation, a thermally activated rearrangement of atoms in the amorphous structure [2] . Most of the studies on resistance drift are based on experiments at or above room temperature, where multiple processes may be occurring simultaneously. In this work, we melt-quenched amorphized GST line cells with widths ~120-140 nm, lengths ~390-500 nm, and thickness ~50nm ( Fig. 1 ) and monitored the current-voltage (I-V) characteristics using a parameter analyzer ( Fig. 2 ) in 85 K to 350 K range. We extracted the drift co-efficient from the slope of the resistance vs. time plots (using low-voltage measurements) and observed resistance drift in the 125 K -300 K temperature range ( Fig. 3 ). We found an approximately linear increase in drift coefficient as a function of temperature from ~ 0.07 at 125 K to ~ 0.11 at 200 K and approximately constant drift coefficients in the 200 K to 300 K range ( Fig. 3 inset). These results suggest that structural relaxations alone cannot account for resistance drift, additional mechanisms are contributing to this phenomenon [5] , [6] . 

Herein, logic function implementations are computationally demonstrated using lateral and vertical multicontact phase‐change devices integrated with complementary metal–oxide–semiconductor (CMOS) circuitry, which use thermal cross‐talk as a coupling mechanism to implement logic functions at smaller CMOS footprints. Thermal cross‐talk during the write operations is utilized to recrystallize the previously amorphized regions to achieve toggle operations. Amorphized regions formed between different pairs of write contacts are utilized to isolate read contacts. Typical expected reduction in CMOS footprint is ≈50% using the described approach for toggle‐multiplexing, JK‐multiplexing, and 2 × 2 routing. The switching speeds of the phase‐change devices are in the order of nanoseconds and are inherently nonvolatile. An electrothermal modeling framework with dynamic materials models is used to capture the device dynamics, and current and voltage requirements.